Flow Chart for DSP Modules
Kindly Follow this Flow Chart for all the DSP Modules
Kindly Follow this Flow Chart for all the DSP Modules
Lecture 1 :Introduction to Digital Signal Processors
Document(s) to refer : The first PDF document about the Features and Architecture of a general DSP and BlackFin 609 in the next page.
1 Introduction to Digital Signal Processors
This video provides a brief introduction to Digital Signal Processor (DSP) Architecture, the major differences and similarities between a DSP and a data processor. A description about the basic features and functionality of a DSP is also given.
1.1Introduction to Digital Signal Processors
More about DSP features - Two Memory architectures - Von Neuman and Harvard. Description about CISC Architecture
1.2 Introduction to Digital Signal Processors
This video section covers RISC Architecture, a summary of DSP features and Introduction to BlackFin 609
1.3 Introduction to Digital Signal Processor
Detailed account on BlackFin 609 processor Architecture
1.4 Introduction to Digital Signal Processors
More about architecture and features of BlackFin 609 - Q and A session
Lecture 2 :Blackfin 609 Architecture - I
Document(s) to refer : Lecture 2 PDF provided in the next page
2 Blackfin 609 Architecture - I
This video section elucidates the addressing modes, modulo arithmetic and execution control
2.1Blackfin 609 Architecture- I
In this video section, you will learn about the registry set and ALU capabilities of BF609
2.2Blackfin 609 Architecture- I
This section covers the MAC capabilities, logical and shift operations of BF609 and also a description of cache organization and Data Address Generator(DAG) units.
2.3Blackfin 609 Architecture - I
Detailed account on memory architecture of BF609
Lecture 3 :Blackfin 609 Architecture - II
Document(s) to refer : Lecture 3 PDF provided in the next page
3 Blackfin 609 Architecture - II
Introduction to pipelining - Types of pipelining and hardware looping
3.1 Blackfin 609 Architecture- II
Description about Data and Instruction level Parallelism and DMA capabilities of BF609
Lecture 4: BF609 Instruction Set
Documenta(s) to refer : Instruction set PDF provided in the next page
4.1 : Instruction set of BF609
Introduction to BF609 Instruction set - Review of BF609 registry set - Load Instructions
4.2 : Instruction set of BF609
This section covers the store, move instructions and logical operations
4.3 : Instruction set of BF609
This section describes the arithmetic and shift operations
4.4 : Instruction set of BF609
This section details the logical shift operation, Control Code bit management, Bit operations and Circular Addressing
BF 609 Instruction Set
Sample Coding
In this Video, a sample code will be taught on how to program and debug remotely using eclipse IDE.
Problem Sheet PDF
Find the problem sheet, containing few basic questions based on the BF609 instruction set. Finish these problems before proceeding with the succeeding modules.
Quiz I
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1. Write a program to store 16-bit LSBs of the input array (containing five 32-bit numbers) with sign extension in an output array (containing five 32-bit numbers)
Example:
Sample input & output
Input array = {0xF0F02828, 0xAA67F444, 0x1DB31234, 0xABCD6DF0, 0x45988777}
Output array = {0x00002828, 0xFFFFF444, 0x00001234, 0x00006DF0, 0Xffff8777}
Repeat the experiment for storing the result with zero extension.
2. Write a program to fetch every 2nd element of an input array (8 elements) and store them in an output array twice (use Circular addressing).
Example:
Sample input & output
Input array = {0x2828, 0x4444, 0x1234, 0x6DF0, 0x7777, 0x0EEEE, 0x1B11, 0x5111}
Output array = {0x2828, 0x1234, 0x7777, 0x1B11, 0x2828, 0x1234, 0x7777, 0x1B11}
3. There are two arrays of size 9 (each element 16-bits wide). Write a program to perform the following:
1) “AND” the first element of both the arrays
2) “OR” the second element of both the arrays
3) “NOT” the third element of first array
4) Find absolute value of the third element of second array .( Use “abs” after sign extending to 32 bit value)
5) “ADD” the fourth element of both the arrays
6) “SUBTRACT” the fifth element of the second array from the fifth element of first array.
7) Multiply the sixth element of both arrays in signed integer format and saturate the result to 16.0 precision in destination register half. (Use (IS) option).
8) Multiply the seventh element of both arrays in signed fraction format and saturate the result to 1.15 precision in destination register half.
9) Add 0x25 to the eighth element of first array. (Use Add Immediate instruction “ =”).
10) Find 2’s complement of the eighth element of the second array.(Use Negate instruction “-“ after sign extending it to 32 bits).
11) Left Shift the 9th element of first array by 3 bits. (use shift instruction “<<=”)
12) Right Shift the 9th element of second array by 2 bits. (use shift instruction “>>=”) Store the results in an array of size 8 (each element 16-bits wide).
Example:
Sample input & output
Input array1 [9] = {0x2828, 0xA167, 0x1DB3, 0x80F0, 0x45AB, 0xFFF1, 0x56DE, 0x1111, 0x0020}
Input array2 [9] = {0x7777, 0x5000, 0x8678, 0x4598, 0x432A, 0xFFF0, 0x0680, 0xD444, 0x0040}
Output array [12] = {0x2020, 0xF167, 0xE24C, 0x7988, 0xC688, 0x0281, 0x00F0,0x0469, 0x1136, 0x2BBC, 0x0100, 0x0010}
4. Write a program to perform 3x3 Matrix multiplications between two arrays and store the output in an array of 9 elements each 16 bits wide. Use Accumulator to perform the multiplication. Write the program in generic form so that it can be easily modified for matrices of different dimensions.
Note: You can only declare a single dimension array. The first 3 elements of the array belong to first row, the next 3 elements to the second row and the last 3 elements to the third row.
Example:
Sample input & output
Input array1 [9] = {1,2,3,2,3,1,3,1,2};
Input array2 [9] = {1,2,3,2,3,1,3,1,2};
Output array [9] = {0x000E,0x000B, 0x000B, 0x000B, 0x000E, 0x000B, 0x000B, 0x000B, 0x000E };
3. Working on Program Flow -CC management -Bit operations
5. Write a program to separate the positive and negative numbers of an array (containing eight 16-bit numbers) and perform the following operations. For positive numbers, “CLEAR” bit 7 and bit 11. For negative numbers, “SET” bit 4 and “TOGGLE” bit 8. Store the results in two different arrays.
Example:
Sample Input and Output
Input array = {0x2828, 0xC444, 0x1234, 0x2F02, 0x7777, 0xEFFE, 0xABCD, 0x5D9F}
Output array1 = {0xC554, 0xEEFE, 0xAADD}
Output array2 = {0x2028, 0x1234, 0x2702, 0x7777, 0x551F}
Assignment not available
Forum for Digital Signal Processing Instruction Set
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Lecture 5: Convolution
Document(s) to refer: Convolution Theory PDF given in the next page
5.1 Convolution
This video section provides an overview of a Linear Time Invariant (LTI) system
5.2 Convolution
This section discusses about the Discrete LTI system
5.3 Convolution
Impluse response of a LTI system
5.4 Convolution
The main idea behind convolution and derivation of the formula
5.5 Convolution
Detailed discussion about Input side and Output side convolution algorithms
Lecture 5.A Convolution Implementation
Document(s) to refer : Convolution Objective and Procedure PDF available in the next page
This video explains the implementation of input and output side algorithm for convolution
Quiz II
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Module 2: FIR filter using input and output side based convolutions
For the given input signal Input signal[35]: {0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1e5a, 0x2ccc, 0x24c0, 0x0ccc, 0xf4d8, 0xeccc, 0xfb3f, 0x1999, 0x37f3, 0x4666, 0x3e5a, 0x2666, 0x0e72, 0x0666, 0x14d8, 0x3333, 0x518d, 0x6000, 0x57f3, 0x4000, 0x280c, 0x1fff, 0x2e72, 0x4ccc, 0x4ccc, 0x4ccc, 0x4ccc, 0x4ccc, 0x4ccc}
1. Low pass filter using the input side based algorithm
System Response[21]={ 0x0000, 0x0166, 0x02fe, 0x04b5, 0x0675, 0x0826, 0x09af, 0x0afc, 0x0bf9, 0x0c97, 0x0ccc, 0x0c97, 0x0bf9, 0x0afc, 0x09af, 0x0826, 0x0675, 0x04b5, 0x02fe, 0x0166, 0x0000 }
2. High pass filter using the output side based algorithm:
System Response: {0x9999, 0x6666} All the signals are of the type 16 bit signed fraction. Plot and observe the graph for input and output signal.
Assignment not available
Forum for Digital Signal Processing Convolution
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Lecture 6
Document(s) to refer: A-Law coding theory PDF
This lecture explains A-Law speech coding.
Quiz - III
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Module 3: A-Law companding (encoding and decoding) on the recorded speech
1. A-Law companding (encoding)
Sample Input &Output:
Input: 0x001F,0x003F,0x007f,0x00ff,0x01ff,0x03ff,0x07ff,0x0fff,0x1fff;
2. A-Law companding (decoding)
Sample Input & Output:
Input: 0x0F,0x1F,0x2f,0x3f,0x4f,0x5f,0x6f,0x7f,0x81
Assignment not available
Forum for Digital Signal Processing - Speech Coding
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DSBSC & SSBSC
In this module, you will learn about two modulation techniques- DSB-SC and SSB-SC and their implementation in Blackfin DSP.
7.1.a. Theory Lecture
7.1.b. Theory Lecture
7.1.c. Theory Lecture
Implementation
Quiz -IV
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To implement DSBSC & SSBSC (both upper & lower sideband) modulation for the given message signal.
m(t) = sin ( 20 π t )
c(t) = sin ( 100 π t )
Assignment not available
Forum for DSBSC and SSBSC
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In this Section you will learn about Echo Cancellation
Implementation
Quiz - V
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1. Perform echo cancellation using the LMS algorithm for the cases given below
2. Perform adaptive channel equalization using the LMS algorithm for the cases given below
Assignment not available
Forum for Echo Cancellation
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In this lecture, the theory behind the Fast Fourier Transform (FFT) is explained.
1. To write a C program to compute a 8-point Fast Fourier Transform given a
real sequence of length 8
1.1 Additional Exercise
Note: N will be a power of 2
Assignment not available
Forum for FFT
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In this video Section, you will learn about Image Restoration
How to Implement Image Restoration ?
Quiz - VII
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Forum for Image Restoration
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In this Video Section, you will learn about DCT
How to Implement DCT?
Quiz - VIII
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Forum for DCT
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