Fundamentals of Small Signal Analysis

Relevant Course: Analog Circuits, Electronic Circuits

Relevant Department: Electrical Engineering

Relevant Semester: 5th but can be done in any semester

Pre- requisite : Knowledge in Taylor Series

Course Description & Outline :

     This Module will introduce the principle behind small s ignal analysis of analog electronic circuits.

a. Motivation : Why small signal analysis ?

b. Small signal analysis of a 1 port nonlinear element: diode example, notion of operating point.

c. What is a small signal ?

d. Small signal representation of a 2 port nonlinear element : examples of MOS Transistors and BJTs

e. Calculating the quiescent operating point and small signal equivalent of MOS/BJT

f. Small signal analysis of simple amplifier structures.

Schedule for Lecture Delivery

Session 1 : 14-Aug-2015 ( 2-4 pm)

Session 2 :  25-Aug-2015 ( 2-4 pm)

Session 3 :  26-Aug-2015 ( 2-4 pm)

Teacher Forum

Introduction

1.1   Linear Networks

A network is said to be linear if it is both homogenous and additive. Consider a   system shown in Fig. 1.1. 

The system produces outputs Y1, Y2 for the inputs X1, X2, respectively. For this system to be linear it has to satisfy the condition,

For a zero input, the output of the system must be zero. If both these conditions are satisfied, the system is said to be a linear system.

Example

For the transfer characteristics given in Fig. 1.2, Y1 and Y2 are outputs for the inputs X1 and X2, respectively

               

When X1 X2 is applied to the system, the output is supposed to be Y1 Y2,

which is equal to 4.5, but the actual output obtained from its characteristics is for X1 X2 = 1 is 2.5. Hence, the system is not linear.
             Linear systems are important because of the fact that the response of the system to one input is sufficient to find  response of the same for all possible inputs. Generally, impulse response is used to characterize a system. All practical systems are non-linear.

1.2 A Simple Non Linear System                                               

  

Fig 1.3: A Simple non linear system 

A simple non linear system, shown in Fig. 1.3, consists of a resistor R1 and a diode D1 connected in series with a voltage source V1. Applying kirchoff’s voltage law in this loop we get,

The current through the diode I is given by the equation,

It can be seen from Eq.(1.6) that the system is non linear. The voltage is non linearly related to the current in the loop.

1.2.1 Incremental linearity

Even though the actual input and output of a system are related in a non linear fashion, an incremental change in input can always be related to incremental change in the output in a linear way as long as the incremental change is small.

For obtaining the absolute value of current and voltage of an element, first the  operating point has to be found. This has to be followed by deriving an incremental equivalent circuit. The absolute values of current and voltage can then be found by  adding quiescent value of current/voltage with incremental value of current/voltage.

Total voltage across the diode = Quiescent voltage Incremental voltage.The incremental equivalent circuit is as shown below.

Figure 1.8 Incremental  equivalent circuit

1.2.2 Notion of incremental linearity in case of a network   with more than one non linear element

Consider the network shown in Fig. 1.9. It has three non linear elements E1,E2,E3. V1 , V2 , V3 are voltages across the elements E1, E2, E3 respectively.I1 ,  I2, I3 are   currents through the elements E1, E2, E3 respectively.

Now, when small signals vA and vB are added to the sources VA and vB, respectively, the currents will change from I1 ,  I2 to I1 i1, I2 i2 respectively. The   voltages V1, V2, V3 will change to V1 v1, V2 v2, V3 v3 respectively. Replacing the   elements E1,E2,E3 with voltage sources equal to V1 v1, V2 v2, V3 v3 respectively, we get an equivalent circuit as shown in the Fig. 1.10.

Applying the Eqs.( 1.19, 1.20), the circuit the sources V1, V2, V3 can be elliminated.

In order to find the incremental equivalent network, the quiescent currents I1, I2, I3 must be eliminated. For this purpose, current sources are carefully added   across each branch such that the node voltages are not modified.

The incremental equivalent network of the circuit is shown in Fig. 1.14. It   can be seen that, like absolute   node voltages and branch currents, the incremental node voltages and branch currents also follow Kirchoff's current law and Kirchoff's voltage law.

1.2.3 Incremental equivalents

The characteristics of an independent voltage source is as shown in Fig. 1.15. For a small change in current, the voltage supplied by the source does not change. Hence, the incremental equivalent of an independent voltage source is a short circuit.

The characteristics of an independent current source is as shown in Fig. 1.16.For  a small change in   voltage, the current supplied by the source does not change. Hence, the incremental equivalent of an independent current source is an open circuit. 

Definition for a small signal Consider a non linear element which has following

1.2.4 Nonlinear two port network

Consider a non linear two port network shown in Fig. 1.19 with following relations.

1.3 Amplifiers

Amplifiers are two port networks which are used to amplify weak or attenuated   signals. An amplifier is connected to the source, Vs on one side which has an internal   resistance, RS and to a load, RL on the other side. Ideally, the gain of an amplifier,

Lecture Videos for Session 1

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Lecture Videos for Session 2

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MOS Field Effect Transistor

From Eqs.(1.40) and (1.53) in chapter 1, we have,

From Eq.(2.4), it is clear that the output can lie in first and third quadrants.The output characteristics will be as shown in Fig. 2.1.

Figure 2.1 : Required output Characteristic 

2.1 NMOS

An NMOS transistor has four terminals namely gate, source, drain and body. Body is usually connected to the source for normal applications. For now, it is sufficient to consider the NMOS as a three terminal device.

Figure 2.2: Various symbols for NMOS.

The drain current , ID of an NMOS is given by 



2.2 Common source amplier


In chapter 1, we have derived the Y parameters of an ampliFIer considering it to be a two port network. In Fig. 2.4, the black box is replaced with an NMOS transistor, with the signal applied at input and output taken from port 2 which is across RL.

Figure 2.4: Two port network replaced with MOS transistor.

The circuit shown in Fig. 2.4 cannot function as an amplier until it is biased in the saturation region. The NMOS is in saturation region when VDS is very high.

Figure 2.5: circuit in figure 2.4 with DC bias.

From Eqs.(1.53), (2.127), we have, y11 = 0; y12 = 0; y21 = gm and y22 = 0. The corresponding small signal equivalent circuit is given in Fig. 2.7.

In Fig. 2.5, the transistor is biased with the help of two diffierent supply voltages. The biasing can be efficiently done by utilizing a single supply and a voltage divider as shown in Fig. 2.8.

The next step is to connect the small signal at the appropriate place without changing the bias of the circuit. If the small signal voltage is simply connected to the gate terminal through a source resistance, it will modify the bias, as a DC current will flow through RS.

In this configuration, as the source of the transistor is common to both input and output, it is called a common source amplifier. 

Note: y12 = 0 means that, the changes in port 2 does not influence a change in port 1. In this case, vgs is the cause and id is the effect. It is not possible to pump a current, ID through drain and get a voltage, VGS at gate.

2.2.1 Swing limits of a common source amplifier

The voltage across drain and source is given by,

The absolute voltage at vo will be only the incremental voltage vds.

As seen in Fig. 2.13, during the positive half of the cycle, as vs increases, vGS increases and vDS decreases. vA is the amplitude of the small signal, vs. The transistor will remain in saturation region as long as vDS < vGS - VT .

From Fig. 2.14, it can be seen that if vA is made to keep increasing, at some point of time vDS will go 1VT below vGS. The limit for vA to ensure the MOSFET remains in saturation during the positive half cycle is given by vAmax1.

During the negative half of the cycle, as vs decreases, vGS decreases and iD also decreases as shown in Fig. 2.15. If vA is kept on increasing, then eventually iD

will become zero. The transistor enters cutoff region. The transconductance, gm of the MOSFET also becomes zero. 

So, it is evident that if vA keeps increasing beyond vAmax1 the transistor will enter the linear region.

From Eq.(2.127), (2.26), it can be seen that gm in triode region is much smaller than gm in saturation region. Thus when vA is increased beyond vAmax1 during the positive half cycle the output gets distorted as shown in Fig. 2.16.

During negative half cycle, when vA reaches vAmax2, the drain current, iD becomes zero. So the transistor is cutoff.

So the minimum value of vAmax1, vAmax2 will be the maximum permissible  input amplitude. Fig. 2.20 depicts various regions of operation along the locus of the operating point.

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