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Table of contents
1 Course Outline
1.1 Teacher Forum
2 Organization
2.1 Trigger flip - flop
2.2 Flip - Flop Excitation Tables
2.3 Counters
2.4 Analysis of Clocked Sequential Circuits
2.5 Counter Design Using D-flip flop
2.6 Counter with Unused States
2.7 Lecture Notes for Session 1
2.8 Lecture Videos - Session 1
2.9 Forum for Organization
3 Organization
3.1 Mealy Sequential Network Design
3.2 Moore Sequential Network Design
3.3 Equivalent Sequential Circuits
3.4 Lecture Notes for Session 2
3.5 Lecture Videos - Session 2
3.6 Forum for Organization
4 Memory
4.1 Memory Decoding
4.2 Address Multiplexing
4.3 ASM - Algorithmic State Machine Charts
4.4 ASM Charts Realization
4.5 Asynchronous Sequential Circuits
4.6 State Table Reduction using an Implication Table
4.7 Lecture Notes for Session 3
4.8 Lecture videos for Session 3
4.9 Forum for Memory
4.10 Quiz
5 Assignment - Proctored
6 Proctored Quiz
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